The present invention relates to a phase locked loop circuit and a control method thereof.
A PLL (Phase Locked Loop) circuit, which generates an output clock in synchronization with an input clock, has been known widely.
In an LSI (Large scale integration) for mobile applications in particular, a PLL circuit may commonly use an original vibration oscillator for generating an input clock with other circuits for the purpose of reducing power consumption. Further, the PLL circuit may selectively use one of a plurality of original vibration oscillators that is operated.
As stated above, the operation of the PLL circuit is typically stopped during a period in which the input clock supplied to the PLL circuit is switched. In this case, however, it is also required to stop the operation of a circuit connected to a subsequent stage of the PLL circuit. Hence, it is required to design the circuit connected to the subsequent stage of the PLL circuit such that even the stop of the PLL circuit does not cause any problem. In order to avoid such a situation, a PLL circuit has been required that is capable of generating an output clock with maintained desired frequency without stopping the operation even when the input clock is switched.
One solution to meet this demand is disclosed in Japanese Unexamined Patent Application Publication No. 2008-60895. FIG. 6 shows a PLL circuit (phase locked loop circuit) 101 disclosed in Japanese Unexamined Patent Application Publication No. 2008-60895. As shown in FIG. 6, the PLL circuit 101 includes a selector 103, a 1/m frequency divider 104, a 1/n frequency divider 105, switch circuits 106a and 106b, a phase difference detector 107, a low-pass filter 108, and a voltage controlled oscillator 109. Further, a control circuit 102 is also shown in FIG. 6.
In the PLL circuit 101, a switching operation of an input clock is controlled based on each control signal supplied from the control circuit 102. The selector 103 selects one of a clock f1 and a clock f2 as an input clock, and outputs the selected clock to the 1/m frequency divider 104. The 1/m frequency divider 104 outputs a first frequency divided clock that is obtained by dividing the input clock to the switch circuit 106a. The switch circuit 106a outputs one of a constant voltage and an inverting signal of the first frequency divided clock that is selected based on a control signal Mask to the phase difference detector 107. The 1/n frequency divider 105 outputs a second frequency divided clock obtained by dividing an output clock fo generated by the voltage controlled oscillator 109 to the switch circuit 106b. The switch circuit 106b outputs one of the constant voltage and an inverting signal of the second frequency divided clock that is selected based on the control signal Mask to the phase difference detector 107. The phase difference detector 107 generates a current based on the phase difference of the two input signals. The low-pass filter 108 generates a voltage (voltage of the node N1) according to the current output from the phase difference detector 107. Then the voltage controlled oscillator 109 generates the output clock fo of the frequency based on the voltage of the node N1.
In the PLL circuit 101, when the input clock is switched, the switch circuits 106a and 106b are first set to output a predetermined voltage to the phase difference detector 107. Thus, the voltage variation in the node N1 is suppressed. In this state, the input clock is switched by the selector 103. Further, in this state, the 1/m frequency divider 104 and the 1/n frequency divider 105 are reset, and the frequency dividing ratios of the 1/m frequency divider 104 and the 1/n frequency divider 105 are changed to the ratios that correspond to the input clock after switching. Accordingly, it is possible to switch the input clock while keeping the voltage controlled oscillator 109 self-running state and keeping the state in which disturbance of the waveform of the output clock fo is suppressed. Accordingly, the PLL circuit 101 generates the stable output clock fo with maintained desired frequency without stopping the operation even when the input clock is switched.